This invention relates generally to the field of regulated power sources and more specifically, to a method and apparatus for improving the response of switching regulators to load transients.
FIG. 1 depicts, at a high level, a system 10 known to the prior art for controlling a switching regulator to regulate an output voltage. The system includes a PWM module 14, a first comparator 18, a second comparator 22, a first logic element 26 and a second logic element 30. The output of the second logic element 30 controls a switch 34 of a switching regulator. The PWM module 14 generates a pulse width modulated command signal to control the switch 34. Whenever the first comparator 18 detects that the output voltage 38 goes out of range (i.e., decreases below a first predetermined acceptable level), the first comparator 18, via logic element 30, rapidly overrides the control signal generated by the PWM module 14 and controls the switch 34 until the out of range condition ends. Similarly, whenever the second comparator 22 detects that the output voltage 38 goes out of range (i.e., increases above a second predetermined acceptable level), the second comparator 22, via logic elements 26 and 30, rapidly overrides the control signal generated by the PWM module 14 and controls the switch 34 until the out of range condition ends. This substantially immediate exit from the PWM control can lead to undesirable effects in the regulated output voltage.
It is an object of this invention to synchronize the action taken by the out-of-range detection circuits with one or more predefined events. In one aspect, the invention relates to a method of controlling a switching regulator to regulate an output voltage. The method includes receiving a first enable signal and a second enable signal, comparing a feedback voltage representative of the output voltage to a first reference voltage and generating a first limit signal in response thereto, and generating, in response to the first enable signal, a close switch command if the first limit signal indicates that the feedback voltage is less than the first reference voltage. The method further includes comparing the feedback voltage to a second reference voltage and generating a second limit signal in response thereto, and generating, in response to the second enable signal, an open switch command if the second limit signal indicates that the feedback voltage is greater than the second reference voltage.
In one embodiment, the method includes comparing the feedback voltage to a third reference voltage and generating a threshold signal in response thereto, and inhibiting the close switch command if the threshold signal indicates that the feedback voltage is greater than the third reference voltage. In another embodiment, the method includes generating a switch control signal. In another embodiment, the step of generating the switch control signal further includes receiving a clock signal, asserting a first state of the switch control signal in response to the clock signal, and comparing the feedback voltage to a fourth reference voltage and generating a difference signal in response thereto. The step of generating the switch control signal also includes comparing the difference signal and a timed ramp signal and asserting a second state of the switch control signal in response to the comparison of the difference signal and the timed ramp signal. In another embodiment, the method includes generating the first enable signal in response to the switch control signal. In another embodiment, the method includes generating the second enable signal in response to the clock signal.
In another embodiment, the method includes receiving a switch type signal having a first state and a second state. In another embodiment, the method includes converting the switch control signal into a drive signal compatible with a p-channel switching device in response to the first state of the switch type signal and converting the switch control signal into a drive signal compatible with a n-channel switching device in response to the second state of the switch type signal. In another embodiment, the method includes using the switch control signal to control a synchronous switching regulator. In another embodiment, the method includes generating the first enable signal in response to a logical combination of a plurality of regulator signals. In another embodiment, the method includes generating the second enable signal in response to a logical combination of the plurality of regulator signals.
In another aspect, the invention relates to a method of controlling a switching regulator to regulate an output voltage. The method includes receiving an enable signal, comparing a feedback voltage representative of the output voltage to a first reference voltage and generating a limit signal in response thereto, and generating, in response to the enable signal, a close switch command if the limit signal indicates that the feedback voltage is less than the first reference voltage. In one embodiment, the method includes comparing the feedback voltage to a second reference voltage and generating a threshold signal in response thereto, and inhibiting the close switch command if the threshold signal indicates that the feedback voltage is greater than the second reference voltage.
In another embodiment, the method includes generating a switch control signal. In another embodiment, the step of generating the switch control signal also includes receiving a clock signal, asserting a first state of the switch control signal in response to the clock signal, and comparing the feedback voltage to a third reference voltage and generating a difference signal in response thereto. The method further includes comparing the difference signal and a timed ramp signal and asserting a second state of the switch control signal in response to the comparison of the difference signal and the timed ramp signal. In another embodiment, the method includes generating the enable signal in response to the switch control signal.
In another embodiment, the method includes receiving a switch type signal having a first state and a second state. In another embodiment, the method includes converting the switch control signal into a drive signal compatible with a p-channel switching device in response to the first state of the switch type signal and converting the switch control signal into a drive signal compatible with a n-channel switching device in response to the second state of the switch type signal. In another embodiment, the method includes using the switch control signal to control a synchronous switching regulator. In another embodiment, the method includes generating the enable signal in response to a logical combination of a plurality of regulator signals.
In another aspect the invention relates to a method of controlling a switching regulator to regulate an output voltage. The method includes receiving an enable signal, comparing a feedback voltage representative of the output voltage to a first reference voltage and generating a limit signal in response thereto, and generating, in response to the enable signal, an open switch command if the limit signal indicates that the feedback voltage is greater than the first reference voltage. In one embodiment, the method includes generating a switch control signal. The step of generating the switch control signal includes receiving a clock signal, asserting a first state of the switch control signal in response to the clock signal, and comparing the feedback voltage to a second reference voltage and generating a difference signal in response thereto. The step of generating the switch control signal further includes comparing the difference signal and a timed ramp signal and asserting a second state of the switch control signal in response to the comparison of the difference signal and the timed ramp signal.
In another embodiment, the method includes generating the enable signal in response to the clock signal. In another embodiment, the method includes receiving a switch type signal having a first state and a second state. In another embodiment, the method includes converting the switch control signal into a drive signal compatible with a p-channel switching device in response to the first state of the switch type signal and converting the switch control signal into a drive signal compatible with a n-channel switching device in response to the second state of the switch type signal. In another embodiment, the method includes using the switch control signal to control a synchronous switching regulator. In another embodiment, the method includes comprising generating the enable signal in response to a logical combination of a plurality of regulator signals.
In another aspect, the invention relates to a system for controlling a switching regulator to regulate an output voltage. The system includes a main control module, a high limit module, a low limit module and an output logic module. The main control module includes a main control module output terminal, a main control module input terminal configured to receive a feedback voltage representative of the regulated output voltage and a main control module clock terminal configured to receive a master clock signal. The main control module further includes a main control module ramp input terminal configured to receive a timed ramp signal and a reference input terminal configured to receive a first reference signal representative of a regulation value of the feedback voltage. The high limit module includes an output terminal, a first input terminal in communication with the main control module input terminal, a reference input terminal configured to receive a second reference signal representative of a high limit and a timing input terminal in communication with the main control module clock terminal. The low limit module includes an output terminal, an input terminal in communication with the main control module input terminal, a first reference input terminal configured to receive a third reference signal representative of a low limit and a timing input terminal in communication with the main control module output terminal. The output logic module includes a first input terminal in communication with the main control module output terminal, a second input terminal in communication with the high limit module output terminal, a third input terminal in communication with the low limit module output terminal, and an output terminal for providing a switch command signal to control the switching regulator.
In one embodiment, the low limit module includes a first comparator and a flip-flop. The first comparator includes a first input terminal in communication with the first reference input terminal of the low limit module, a second input terminal in communication with the input terminal of the low limit module and an output terminal. The flip-flop includes an input terminal in communication with the output terminal of the first comparator, a timing input terminal in communication with the timing input terminal of the low limit module, a reset terminal and an output terminal in communication with the output terminal of the low limit module. In another embodiment, the low limit module includes a second reference input terminal configured to receive a fourth reference signal representative of a threshold limit. In another embodiment, the low limit module includes a second comparator. The second comparator includes a first input terminal in communication with the second reference input terminal of the low limit module, a second input terminal in communication with the input terminal of the low limit module and an output terminal in communication with the reset terminal of the flip-flop.
In another embodiment, the high limit module includes a comparator and a flip-flop. The comparator includes an output terminal, a first input terminal in communication with the reference input terminal of the high limit module and a second input terminal in communication with the first input terminal of the high limit module. The flip-flop includes an input terminal in communication with the output terminal of the comparator, a timing input terminal in communication with the timing input terminal of the high limit module and an output terminal in communication with the output terminal of the high limit module. In another embodiment, the output logic module includes an AND gate and an OR gate. The AND gate includes an output terminal, a first input terminal in communication with the first input terminal of the output logic module and an inverting input terminal in communication with the second input terminal of the output logic module. The OR gate includes a first input in communication with the third input terminal of the output logic module, a second input terminal in communication with the output terminal of the AND gate and an output terminal in communication with the output terminal of the output logic module.
In another embodiment, the main control module includes an amplifier, a compensation network, a comparator and a flip-flop. The amplifier includes an output terminal, a first input terminal in communication with the main control module input terminal and a second input terminal in communication with the reference input terminal of the main control module. The compensation network includes a first terminal in communication with the output terminal of the amplifier and a second terminal in communication with a voltage node. The comparator includes an output terminal, a first input terminal in communication with the output terminal of the amplifier and a second input terminal in communication with the main control module ramp input terminal. The flip-flop includes a set terminal in communication with the main control module clock terminal, a reset terminal in communication with the output terminal of the comparator and an output terminal in communication with the main control module output terminal. In another embodiment, the system includes a capacitive element electrically connected between the first and second terminals of the compensation network. In another embodiment, the system includes a filter in communication with the first input terminal of the high limit module. In another embodiment, the system includes a filter in communication with the first input terminal of the low limit module.
In another aspect, the invention relates to a system for controlling a switching regulator to regulate an output voltage. The system includes a means for receiving a first enable signal and a second enable signal, a means for comparing a feedback voltage representative of the output voltage to a first reference voltage and generating a first limit signal in response thereto, and a means for generating, in response to the first enable signal, a close switch command if the first limit signal indicates that the feedback voltage is less than the first reference voltage. The system further includes a means for comparing the feedback voltage to a second reference voltage and generating a second limit signal in response thereto, and a means for generating, in response to the second enable signal, an open switch command if the second limit signal indicates that the feedback voltage is greater than the second reference voltage. In one embodiment, the system includes a means for comparing the feedback voltage to a third reference voltage and generating a threshold signal in response thereto, and a means for inhibiting the close switch command if the threshold signal indicates that the feedback voltage is greater than the third reference voltage.
In another aspect, the invention relates to a system of controlling a switching regulator to regulate an output voltage. The system includes a means for receiving an enable signal, a means for comparing a feedback voltage representative of the output voltage to a first reference voltage and generating a limit signal in response thereto, and a means for generating, in response to the enable signal, a close switch command if the limit signal indicates that the feedback voltage is less than the first reference voltage. In one embodiment, the system includes a means for comparing the feedback voltage to a second reference voltage and generating a threshold signal in response thereto, and a means for inhibiting the close switch command if the threshold signal indicates that the feedback voltage is greater than the second reference voltage.
In another aspect, the invention relates to a system of controlling a switching regulator to regulate an output voltage. The system includes a means for receiving an enable signal, a means for comparing a feedback voltage representative of the output voltage to a reference voltage and generating a limit signal in response thereto, and a means for generating, in response to the enable signal, an open switch command if the limit signal indicates that the feedback voltage is greater than the reference voltage.